This invention relates generally to serial communication interfaces and in particular to unidirectional serial communication, and is more particularly directed toward utilizing a read-only serial interface to place a device in a power-down mode.
The popularity of battery-operated equipment, and the demand for smaller devices with longer periods between battery replacement or recharging, has given rise to a need for reducing power consumption in the devices used in such equipment. One technique that has been developed involves supplying full power to a device during periods of so-called xe2x80x9cnormalxe2x80x9d operation, and placing the device in a low power consumption mode (sometimes referred to as xe2x80x9cinactive,xe2x80x9d xe2x80x9cpower down,xe2x80x9d or xe2x80x9csleepxe2x80x9d mode) during intervening non-operating periods.
U.S. Pat. No. 5,619,204 describes an analog-to-digital converter (ADC) with optional low power mode that is controlled by monitoring the state of a xe2x80x9cconversion startxe2x80x9d (CONVST) signal with respect to the conversion completion point. U.S. Pat. No. 5,714,955 (""955 Patent) describes dual function control circuitry for effecting the switchover between operating modes of a serial ADC. The control signals used to trigger this switchover between operating modes are signals associated with the conversion process and not with the serial data transfer.
FIG. 1 is a block diagram of an ADC of the prior art (generally depicted by the numeral 100) that is configured for power-down mode control. A CLK (clock) signal 101 is used to synchronise the conversion operation, and a CONV (conversion) signal 102 is used to initiate the conversion operation. The CLK 101 and CONV 102 signals are provided as inputs to internal control logic 103 that controls operation of the SAR (successive approximation register) and parallel to serial converter logic 104. The serial output data 108 of the device 100 is derived by shifting out the SAR contents serially after the conversion is complete.
The CLK 101 and CONV 102 signals also serve to produce power-down and power-up commands. They thus serve as dual-function pins. However, these signals do not produce these power-up and power-down commands when operating in the usual manner across the serial interface. The manner in which these signals must be asserted with respect to each other is not easily configured over a standard serial interface, and cannot provide power-down and power-up commands when standard serial communication is taking place. Instead, the signals are asserted as shown in the timing diagram of FIG. 2.
When CLK 201 is low, two CONV 202 pulses command the ADC to enter a first power-down mode, in this case a reduced power consumption mode denominated the NAP mode 203. When CLK 201 remains low, two additional CONV 202 pulses are required to place the part in a second power-down mode, in this case the SLEEP mode 204, consuming even less power than the NAP mode 203. The timing of CONV and CLK are not easily generated over a standard serial interface with a microcontroller, and are not available from a DSP in the manner required.
The closest known practice exists in a family of serial ADCs manufactured by Analog Devices, Inc. Shutdown is controlled via the state of xe2x80x9cchip selectxe2x80x9d (CS) when the device is in read-only mode. When CS is low, the device is fully powered up, and when CS is high the device is fully powered down. This means that shutdown is enforced after each conversion, and so the required power-up time must be allowed before each conversion, slowing down the overall throughput of the device.
Conventional ADC circuits typically use a dedicated input in order to implement a power-down function. This requirement for a dedicated input increases the number of lines in the chip package.
Consequently, a need arises for a power-down mode implementation that does not require a dedicated input or complex, multi-line protocol, and does not interfere with device throughput.
These shortcomings of the prior art, and others, are addressed using the shut-down mode programming of the present invention. The read-only serial interface can be used to place an ADC or other integrated circuit device in one or more power-down modes without writing to a control register or using a dedicated shut-down pin. This involves monitoring the state of CS with respect to the system clock (SCLK). After the falling edge of CS, shut-down is detected by checking the point where CS returns to a logic high during the following burst of 16 SCLKs. Subsequent power-up is detected in the same way.
Three modes of operation are provided. These are the Fully-Powered Mode, Partial Power-Down Mode, and Full Power-Down Mode. In the Fully-Powered Mode, all portions of the device are fully powered at all times, so this mode of operation yields fastest device throughput but increased power consumption.
In the Partial Power-Down Mode of operation, power is removed from most portions of the device except when a conversion has been initiated. The Partial Power-Down Mode requires an extra conversion cycle for the first conversion performed, so device throughput is reduced in return for reduced power consumption.
In Full Power-Down Mode, all analog circuitry on the device is powered down. This mode of operation is intended for applications in which power conservation is of the utmost importance. Device throughput is relatively low in Full Power-Down Mode, primarily because of the extended time periods required both to place the device in Full Power-Down and to xe2x80x9cwake it upxe2x80x9d again.
In accordance with the invention, a method is provided for placing a device in a reduced power-consumption mode of operation. The method comprises the steps of initializing a device select signal into a first logic state, asserting the device select signal in a second logic state, and returning the device select signal to the first logic state within a first predetermined time window. In one form of the invention, the step of initializing a device select signal further comprises the step of placing the device select signal into an inactive logic state. The inactive logic state may comprise a HIGH logic state. The step of asserting the device select signal further comprises the step of placing the device select signal into an active logic state, which may comprise a LOW logic state.
In one form of the invention, the device includes a clock signal input and the step of returning the device select signal to the first logic state within a first predetermined time window further comprises the step of returning the device select signal to the first logic state after the occurrence of a first transition of the clock signal, but before the occurrence of a second subsequent transition of the clock signal. The first transition of the clock signal preferably comprises the second falling edge of the clock signal that occurs after assertion of the device select signal in a second logic state, while the second subsequent transition of the clock signal comprises the tenth falling edge of the clock signal that occurs after assertion of the device select signal in a second logic state.
In accordance with another aspect of the invention, the device is restored to fully-powered mode by the additional steps of asserting the device select signal in the second logic state, and returning the device select signal to the first logic state within a second predetermined time window. The second predetermined time window is defined by at least ten falling edges of the clock signal.
In accordance with yet another aspect of the invention, a method is provided for placing an integrated circuit device having a chip select (CS) input and a clock (CLK) input into a reduced power consumption mode of operation. The method comprises the steps of controlling the CS input of the device to place the CS input into an initial inactive logic state, placing the CS input into an active logic state to select the device, and, within a first predetermined time window defined by transitions of the CLK signal, returning the CS input to the initial inactive logic state. The initial inactive logic state may be a HIGH logic state, while the active logic state may be a logic LOW state.
In accordance with a further aspect of the invention, the first predetermined time window defined by transitions of the CLK signal comprises a time window beginning with the second falling edge of the CLK signal that occurs after CS is placed in an active logic state, and ending with the tenth subsequent falling edge of the CLK signal that occurs while CS is in the active logic state. In one form of the invention, the device is restored to fully-powered mode by the additional steps of placing the CS input into the active logic state to select the device, and, within a second predetermined time window defined by transitions of the CLK signal, returning the CS input to the initial inactive logic state. Preferably, the second predetermined time window is defined by at least ten falling edges of the CLK signal.
In accordance with another embodiment of the invention, a device comprises means for detecting logic state transitions at a device select input and a clock input, and means for changing operating mode of the device in response to a predetermined number of logic state transitions at the clock input, occurring between logic state transitions at the device select input. In one form of the invention, the means for detecting logic state transitions at a device select input and a clock input further comprises clock divide logic and counter circuitry coupled to the serial clock signal and the device select signal, the clock divide logic and counter circuitry generating intermediate control signals including a first intermediate control signal that occurs after the second falling edge of the serial clock signal and a second intermediate control signal that occurs after the tenth falling edge of the serial clock signal.
In another aspect of the present invention, the means for changing operating mode of the device places the device in a reduced power consumption mode of operation in response to a first combination of logic state transitions, and restores the device to fully-powered operation in response to a second combination of logic state transitions. The first combination of logic state transitions comprises between two and ten logic state transitions at the clock input, occurring between logic state transitions at the device select input, while the second combination of logic state transitions comprises at least ten logic state transitions at the clock input, occurring between logic state transitions at the device select input.
In accordance with yet another aspect of the invention, an analog-to-digital converter comprises means for converting an analog input signal into a corresponding digital signal in response to a control signal, means for outputting the corresponding digital signal in serial form in response to a serial clock signal, means for generating at least one command signal in response to a number of serial clock signal cycles occurring between changing states of the control signal, and means for applying power to selected portions of the analog-to-digital converter in response to the command signal.
In yet a further aspect of the invention, the means for converting an analog input signal into a corresponding digital signal further comprises a track and hold circuit coupled to the analog input signal, and a successive approximation ADC coupled to the track and hold circuit. The means for outputting the corresponding digital signal further comprises a successive approximation register, a data multiplexer coupled to the successive approximation register and the serial clock signal, and a serial data output coupled to the data multiplexer.
In another form of the invention, the means for generating at least one command signal further comprises clock divider and counter logic coupled to the serial clock signal and the control signal, wherein the clock divider and counter logic generates a plurality of command signals conditioned, at least in part, by the number of serial clock signal cycles occurring between changing states of the control signal. The means for applying power to selected portions of the analog-to-digital converter further comprises control and power management logic coupled to the control signal and the clock divider and counter logic.